# Cascode Amplifier

For one of my analog electronics courses (ELEC 3509 at Carleton University), one of the lab projects was the design of a cascode amplifier. As shown in the schematic below, it is composed of a BJT in the common-emitter (CE) configuration (Q1) followed by a transistor in the common-base (CB) configuration (Q2). While the basic CE emitter amplifier has good gain and input impedance, it suffers from a poor frequency response due to the Miller effect.

A schematic of the cascade amplifier.

The cascode amplifier improves upon the frequency response of the CE amplifier, as will be discussed below. For the project, the given specification was:

 Midband voltage gain (32.72 ± 1.64) V/V Load resistance 22 kΩ Low cutoff frequency (-3 dB) 60 Hz to 200 kHz High cutoff frequency (-3 dB) > 600 kHz Minimum output swing (peak-to-peak) 2 V Maximum total power dissipation 50 mW Collector current (1.0 ± 0.1) mA Supply voltage 15 V

The design process began by producing the small signal model, shown below. The hybrid-pi model was used to model Q1 while the T-model of the BJT was used for Q2. The internal capacitances of the BJTs were included for determining the high-frequency response.

A small signal model of the cascode amplifier.

## Component Values

One of the most important points in designing the component values was ensuring that the signal swing at the emitter of Q2 ( in the small signal model) was small – below 10 mV peak-to-peak. This is because is small (about 25 Ω), so a small signal is required to keep within the linear region of Q2. Since the parallel combination of  and determined the voltage gain of the second stage, the 2 V output swing requirement and maximum 10 mV swing of required that be at least 6.47 kΩ. The closest available nominal resistance of 8.2 kΩ was selected.

Since the transistors were to operate at 1 mA, the emitter of Q2 was at 8.2 V with the selection of . 2 V was allocated for the of Q2, to allow for 1 V of swing while leaving room to prevent saturation. The remaining voltage was divided between  and the of Q1. This was a tradeoff between better operating point stability (if more voltage were allocated to ) or a better high-frequency response. (Increasing for Q1 increases the base-collector depletion region width and thus decreases internal capacitance). 0.47 V was allocated to the emitter resistor, allowing an available 470 Ω resistor to be used.

Lastly, forms a voltage divider at the input and could be used to control the gain of the overall filter. Note that the magnitude of the gain of the amplifier is

This was solved for , which was found to be 12.3 kΩ.

The coupling capacitors were selected so that the low frequency -3 dB cutoff would be at about 100 Hz, within the 60-200 Hz requirement. This requirement was likely imposed so that AC power noise would not be amplified.

## Simulation

Before prototyping, the circuit was simulated in LTSpice. It was found that the signal swing was too great at the emitter of Q2. The overall gain was found to be about 36.5 V/V, which was also too great. was increased to decrease the gain at the first stage, which resolved the first issue; however, the simulated gain became slightly too small. This was temporarily accepted, since it was expected that poor tolerances on components available for implementation would require changing component values anyways. The coupling capacitor values were also modified. The simulation also indicated a high-frequency -3 dB cutoff of 3.5 MHz, which was well above the required 600 kHz.

The simulated frequency response of the cascode amplifier, before component value modifications.

## Implementation

The circuit was implemented on a breadboard, as shown below.

The implementation of the amplifier on a breadboard. I tried to reduce the parasitic capacitances added by the breadboard.

After fine-tuning the circuit, the final component values were:

ComponentDesign valueActual value
$R_1$ (kΩ)5.65.54
R2 (kΩ)2214.83
R3 (kΩ)4755.5
R4 (kΩ)1517.53
RC (kΩ)8.29.81
RE (kΩ)470472
RL (kΩ)2222
CE (μF)2233
CB (μF)110
CIN (μF)2222
COUT (μF)1022

The operating characteristics of the circuit were then measured to ensure compliance to the specification. the midband gain was found to be 31.74 V/V, which was within the specified (32.72 ± 1.64) V/V. The input impedance was measured to be 21.2 kΩ and the output impedance 9.76 kΩ. The low-frequency cutoff was found to be 112 Hz, which is close to the designed 100 Hz. Lastly, the high-frequency cutoff was about 600 Hz, just barely meeting the specification. This is far less than the simulated 3.5 MHz, and is likely due to the capacitances introduced by the breadboard and components, which are not ideal for testing this circuit. Nevertheless, this is an improvement over the single-transistor CE amplifier that was tested in another experiment, which had a high frequency cutoff of 220 kHz.

The measured frequency response of the amplifier was within the specification, which is indicated by the dashed lines. The theoretical (calculated) response calculated before implementation is also shown.

The improvement is thanks to Q2, which acts as a current buffer. The single-transistor CE amplifier suffers from the Miller effect, which causes its internal base-collector capacitance to be multiplied by the gain, which results in a large capacitance and a low high-frequency cutoff. The current buffering of Q2 causes the base-collector voltage gain of Q1 to be small, so the Miller effect does not significantly increase the effective internal capacitance of Q1. Since Q2 acts as current buffer, it also has a good high output resistance. Thus, adding Q2 to the simple CE amplifier with direct coupling produces an an amplifier with significantly better performance.  This is in exchange for the increased complexity of an extra BJT, several resistors, and a capacitor.

Overall, the design met or exceeded all of the specifications.