Category Archives: School

Op-Amp Design and Fabrication

For one of my courses (ELEC 4609 at Carleton University), a major project was the design and fabrication of a CMOS circuit. While a digital circuit such as a pseudorandom sequence generator was a popular choice for other students, I elected to make an op-amp. I started this project with having just studied analyzing BJT op-amps, and now I set out to design a CMOS op-amp. I had little exposure to CMOS at the start of the project so it was fairly ambitious.

The topology I chose was an NMOS-input differential pair followed by a common-source amplifier, with a class-AB output buffer. This is a fairly standard circuit. However, rather than using traditional Miller compensation, I used a form of indirect compensation. As explained by V. Saxena and J. Baker, this solves the problem of the right-half plane (RHP) zero in Miller compensation, which decreases the phase margin and ultimately reduces the unity-gain bandwidth when because a larger compensating capacitor is required. I implemented the indirect compensation using split-length transistors for the PMOS differential pair load and feeding the signal from C_c in between.

Op-amp Circuit

The two-stage op-amp with a class-AB output buffer.

Note that the compensation capacitor is implemented as a MOSFET (M14) with source and drain tied, and operating in inversion. This was used since real capacitors were not available in the CMOS process. I won’t go into the details of the rest of the schematic as it is fairly standard.

Speaking of the CMOS process, most of the fabrication steps were done at Carleton University. It is uncommon for a university to have a fab due to the cost. At Carleton, the minimum gate length is about 4.8 μm, although test have shown that smaller devices can work. This is very large compared to modern CMOS; nevertheless, it’s neat to be able to fabricate on-site. For this project, a silicon-on-insulator (SOI) process was used. While this is more costly than ordinary bulk CMOS, it was used since it can be done with less processing steps. Time was a concern for the project, since only part of the semester was available for fabrication. I was not involved with the fabrication.

SOI has some important advantages over bulk SOI. For example, there is reduced source/drain capacitance (speed improvement), arbitrary biasing of individual transistors (no body effect), and complete immunity to latch-up (since there is an insulator below). In the design, there are no body connections made. The channel region is essentially left floating, but this is OK; remember that it’s insulated from all the other devices. Since the “well” is very shallow, it is nearly or completely depleted, and the gate might not have to modulate a depletion charge at all: V_{Tn}\approx -(E_g/2 - \phi_B) + \Delta V for NMOS and V_{Tp}\approx -(E_g/2 + \phi_B) + \Delta V for PMOS. \Delta V is due to a threshold adjustment implant that is used to adjust the threshold voltages; it is usually used to make them equal in magnitude.

Back to the circuit in question, the final schematic (with device sizes) is shown below. Note that the layout included input protection, which is shown in this schematic (devices M15 and M16). These don’t seem reasonable here, but make sense in the layout.

The op-amp circuit, showing device sizes. Also shown is the input protection, which comprises of devices M15 and M16. M14 is the compensating MOSFET capacitor.

After putting together the schematic, simulating it, and much revision, I moved onto the layout. This was done in L-Edit, which is a tool from the 90s. This is still used since the design rules are available in a format that was made for this software. Throughout the design, I used matching techniques like common-centroid layout and using dummy poly. Long devices were implemented with multiple fingers. See below. To ensure functionality, the circuit was extracted and compared to the schematic using a tool called Tanner Layout Versus Schematic (LVS). This software is able to combine split devices and check that that the layout truly implements the desired schematic.

The final testing of the op-amp was brief, but it was found to be functional. A DC sweep comparing the simulation to reality is shown below.

A DC sweep over the 3 V supply voltage.

Taking the derivative, the DC gain is plotted below. The gain is about 376.6 V/V (51.5 dB), which is less than the simulated value of 958.9 V/V (59.6 V/V). Also, there is an input-referred offset of about 26 mV.

The simulated gain and measured gain.

Lastly, the stability of the op-amp was tested by configuring it as a unity-gain buffer, producing the oscilloscope capture shown below. Since is a replica of the input (as expected for a buffer), the circuit is stable. Note that the oscilloscope is incorrectly calculating the amplitude on Ch4 (1.740 V). By considering that both traces are displayed at 1.00 V/div and both traces have the same height, it is clear that the gain is truly unity.

An oscilloscope capture showing the input and output of the unity-gain buffer.

While the testing verified the basic functionality of the op-amp, much more extensive testing is left to be desired. Perhaps of most importance would a Bode plot indicating the response of the op-amp at different frequencies, and also showing the unity-gain bandwidth product. Other tests should be done to find the common-mode input range and quiescent power dissipation. Nevertheless, the successful testing of the op-amp was a good opportunity to gain experience working in a lab environment and provided satisfying closure to the project.

Cascode Amplifier

For one of my analog electronics courses (ELEC 3509 at Carleton University), one of the lab projects was the design of a cascode amplifier. As shown in the schematic below, it is composed of a BJT in the common-emitter (CE) configuration (Q1) followed by a transistor in the common-base (CB) configuration (Q2). While the basic CE emitter amplifier has good gain and input impedance, it suffers from a poor frequency response due to the Miller effect.

Cascode Amplifier Schematic

A schematic of the cascade amplifier.

The cascode amplifier improves upon the frequency response of the CE amplifier, as will be discussed below. For the project, the given specification was:

Midband voltage gain(32.72 ± 1.64) V/V
Load resistance22 kΩ
Low cutoff frequency (-3 dB)60 Hz to 200 kHz
High cutoff frequency (-3 dB)> 600 kHz
Minimum output swing (peak-to-peak)2 V
Maximum total power dissipation50 mW
Collector current(1.0 ± 0.1) mA
Supply voltage15 V

The design process began by producing the small signal model, shown below. The hybrid-pi model was used to model Q1 while the T-model of the BJT was used for Q2. The internal capacitances of the BJTs were included for determining the high-frequency response.

Cascade Amplifier Small Signal Model

A small signal model of the cascode amplifier.

Component Values

One of the most important points in designing the component values was ensuring that the signal swing at the emitter of Q2 (v_{\pi 2} in the small signal model) was small – below 10 mV peak-to-peak. This is because r_{e2} is small (about 25 Ω), so a small signal is required to keep within the linear region of Q2. Since the parallel combination of R_C and R_L determined the voltage gain of the second stage, the 2 V output swing requirement and maximum 10 mV swing of v_{\pi 2} required that R_C be at least 6.47 kΩ. The closest available nominal resistance of 8.2 kΩ was selected.

Since the transistors were to operate at 1 mA, the emitter of Q2 was at 8.2 V with the selection of R_C. 2 V was allocated for the V_{CE} of Q2, to allow for 1 V of swing while leaving room to prevent saturation. The remaining voltage was divided between V_E and the V_{CE} of Q1. This was a tradeoff between better operating point stability (if more voltage were allocated to V_E) or a better high-frequency response. (Increasing V_{CE} for Q1 increases the base-collector depletion region width and thus decreases internal capacitance). 0.47 V was allocated to the emitter resistor, allowing an available 470 Ω resistor to be used.

Lastly, R_4 forms a voltage divider at the input and could be used to control the gain of the overall filter. Note that the magnitude of the gain of the amplifier is

    \[|A| &= \frac{\beta}{\beta + 1} g_m (R_C||R_L)\frac{R_1||R_2||r_{\pi 1}}{R_1||R_2||r_{\pi 1} + R_4} \]

This was solved for R_4, which was found to be 12.3 kΩ.

The coupling capacitors were selected so that the low frequency -3 dB cutoff would be at about 100 Hz, within the 60-200 Hz requirement. This requirement was likely imposed so that AC power noise would not be amplified.


Before prototyping, the circuit was simulated in LTSpice. It was found that the signal swing was too great at the emitter of Q2. The overall gain was found to be about 36.5 V/V, which was also too great. R_4 was increased to decrease the gain at the first stage, which resolved the first issue; however, the simulated gain became slightly too small. This was temporarily accepted, since it was expected that poor tolerances on components available for implementation would require changing component values anyways. The coupling capacitor values were also modified. The simulation also indicated a high-frequency -3 dB cutoff of 3.5 MHz, which was well above the required 600 kHz.

Simulated Gain

The simulated frequency response of the cascode amplifier, before component value modifications.


The circuit was implemented on a breadboard, as shown below.

The implementation of the amplifier on a breadboard. I tried to reduce the parasitic capacitances added by the breadboard.

After fine-tuning the circuit, the final component values were:

ComponentDesign valueActual value
$R_1$ (kΩ)5.65.54
R2 (kΩ)2214.83
R3 (kΩ)4755.5
R4 (kΩ)1517.53
RC (kΩ)8.29.81
RE (kΩ)470472
RL (kΩ)2222
CE (μF)2233
CB (μF)110
CIN (μF)2222
COUT (μF)1022

The operating characteristics of the circuit were then measured to ensure compliance to the specification. the midband gain was found to be 31.74 V/V, which was within the specified (32.72 ± 1.64) V/V. The input impedance was measured to be 21.2 kΩ and the output impedance 9.76 kΩ. The low-frequency cutoff was found to be 112 Hz, which is close to the designed 100 Hz. Lastly, the high-frequency cutoff was about 600 Hz, just barely meeting the specification. This is far less than the simulated 3.5 MHz, and is likely due to the capacitances introduced by the breadboard and components, which are not ideal for testing this circuit. Nevertheless, this is an improvement over the single-transistor CE amplifier that was tested in another experiment, which had a high frequency cutoff of 220 kHz.

The measured frequency response of the amplifier was within the specification, which is indicated by the dashed lines. The theoretical (calculated) response calculated before implementation is also shown.

The improvement is thanks to Q2, which acts as a current buffer. The single-transistor CE amplifier suffers from the Miller effect, which causes its internal base-collector capacitance to be multiplied by the gain, which results in a large capacitance and a low high-frequency cutoff. The current buffering of Q2 causes the base-collector voltage gain of Q1 to be small, so the Miller effect does not significantly increase the effective internal capacitance of Q1. Since Q2 acts as current buffer, it also has a good high output resistance. Thus, adding Q2 to the simple CE amplifier with direct coupling produces an an amplifier with significantly better performance.  This is in exchange for the increased complexity of an extra BJT, several resistors, and a capacitor.

Overall, the design met or exceeded all of the specifications.

Reverse Engineering of a Tent Peg

During my first year of engineering, I completed an “Introduction to Engineering” course (ECOR 1101) that sampled various topics from mechanical CAD to engineering ethics. For the CAD portion, we were tasked in groups to redesign a simple mechanical component. As a past Scout and backcountry camper, one thing that I thought could be improved is the humble tent peg that is used to prevent a camping tent from shifting around during the night (or blowing away if it’s windy!).

Tent Peg Solid Model

A solid model of the tent peg exported from PTC Creo

My group decided to improve the tent peg by adding a handle for easier removal from the ground. We also added notches along the length of the peg in order to increase the force required to remove it from the ground. I was tasked with modelling the peg, using a parametric CAD software called PTC Creo.

The complex shape of the peg made it a difficult first modelling project. The handle portion presented the greatest challenge in order to make it ergonomic. I decided to make it hollow in order to reduce the amount of material required to manufacture the peg.

If the peg were to be manufactured in large quantities, injection moulding with ABS plastic would be used. For prototyping, 3D printing was used instead. Thus, some constraints were given: maximum dimensions of 5″ x 5″ x 5″ and a maximum volume of 1 cubed inch. Thus, a scale version of the original 10-inch tent peg was produced. The schematic below shows compliance to the size specification. This was successfully 3D-printed using the STL file exported from Creo.

Tent Peg Size Compliance

Compliance to the maximum size was satisfied.