Op-Amp Design and Fabrication

For one of my courses (ELEC 4609 at Carleton University), a major project was the design and fabrication of a CMOS circuit. While a digital circuit such as a pseudorandom sequence generator was a popular choice for other students, I elected to make an op-amp. I started this project with having just studied analyzing BJT op-amps, and now I set out to design a CMOS op-amp. I had little exposure to CMOS at the start of the project so it was fairly ambitious.

The topology I chose was an NMOS-input differential pair followed by a common-source amplifier, with a class-AB output buffer. This is a fairly standard circuit. However, rather than using traditional Miller compensation, I used a form of indirect compensation. As explained by V. Saxena and J. Baker, this solves the problem of the right-half plane (RHP) zero in Miller compensation, which decreases the phase margin and ultimately reduces the unity-gain bandwidth when because a larger compensating capacitor is required. I implemented the indirect compensation using split-length transistors for the PMOS differential pair load and feeding the signal from C_c in between.

Op-amp Circuit

The two-stage op-amp with a class-AB output buffer.

Note that the compensation capacitor is implemented as a MOSFET (M14) with source and drain tied, and operating in inversion. This was used since real capacitors were not available in the CMOS process. I won’t go into the details of the rest of the schematic as it is fairly standard.

Speaking of the CMOS process, most of the fabrication steps were done at Carleton University. It is uncommon for a university to have a fab due to the cost. At Carleton, the minimum gate length is about 4.8 μm, although test have shown that smaller devices can work. This is very large compared to modern CMOS; nevertheless, it’s neat to be able to fabricate on-site. For this project, a silicon-on-insulator (SOI) process was used. While this is more costly than ordinary bulk CMOS, it was used since it can be done with less processing steps. Time was a concern for the project, since only part of the semester was available for fabrication. I was not involved with the fabrication.

SOI has some important advantages over bulk SOI. For example, there is reduced source/drain capacitance (speed improvement), arbitrary biasing of individual transistors (no body effect), and complete immunity to latch-up (since there is an insulator below). In the design, there are no body connections made. The channel region is essentially left floating, but this is OK; remember that it’s insulated from all the other devices. Since the “well” is very shallow, it is nearly or completely depleted, and the gate might not have to modulate a depletion charge at all: V_{Tn}\approx -(E_g/2 - \phi_B) + \Delta V for NMOS and V_{Tp}\approx -(E_g/2 + \phi_B) + \Delta V for PMOS. \Delta V is due to a threshold adjustment implant that is used to adjust the threshold voltages; it is usually used to make them equal in magnitude.

Back to the circuit in question, the final schematic (with device sizes) is shown below. Note that the layout included input protection, which is shown in this schematic (devices M15 and M16). These don’t seem reasonable here, but make sense in the layout.

The op-amp circuit, showing device sizes. Also shown is the input protection, which comprises of devices M15 and M16. M14 is the compensating MOSFET capacitor.

After putting together the schematic, simulating it, and much revision, I moved onto the layout. This was done in L-Edit, which is a tool from the 90s. This is still used since the design rules are available in a format that was made for this software. Throughout the design, I used matching techniques like common-centroid layout and using dummy poly. Long devices were implemented with multiple fingers. See below. To ensure functionality, the circuit was extracted and compared to the schematic using a tool called Tanner Layout Versus Schematic (LVS). This software is able to combine split devices and check that that the layout truly implements the desired schematic.

The final testing of the op-amp was brief, but it was found to be functional. A DC sweep comparing the simulation to reality is shown below.

A DC sweep over the 3 V supply voltage.

Taking the derivative, the DC gain is plotted below. The gain is about 376.6 V/V (51.5 dB), which is less than the simulated value of 958.9 V/V (59.6 V/V). Also, there is an input-referred offset of about 26 mV.

The simulated gain and measured gain.

Lastly, the stability of the op-amp was tested by configuring it as a unity-gain buffer, producing the oscilloscope capture shown below. Since is a replica of the input (as expected for a buffer), the circuit is stable. Note that the oscilloscope is incorrectly calculating the amplitude on Ch4 (1.740 V). By considering that both traces are displayed at 1.00 V/div and both traces have the same height, it is clear that the gain is truly unity.

An oscilloscope capture showing the input and output of the unity-gain buffer.

While the testing verified the basic functionality of the op-amp, much more extensive testing is left to be desired. Perhaps of most importance would a Bode plot indicating the response of the op-amp at different frequencies, and also showing the unity-gain bandwidth product. Other tests should be done to find the common-mode input range and quiescent power dissipation. Nevertheless, the successful testing of the op-amp was a good opportunity to gain experience working in a lab environment and provided satisfying closure to the project.